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Magazine Name : Ieee Journal Of Solid-State Circuits

Year : 2005 Volume number : 40 Issue: 01

A Dual-Core 64-Bit Ultrasparc Microprocessor For Dense Server Applications (Article)
Subject: Chip Multithreading , Coupling Noise
Author: Toshinari Takayanagi      Jinuk Kuke Shin     
page:      07 - 18
Uniform-Phase Uniform-Amplitude Resonant-Load Global Clock Distributions (Article)
Subject: Clock Distribution , Inductance
Author: Steven C. Chen      Kenneth L. Shepard     
page:      102 - 109
A 0.16-2.55-Ghz Cmos Active Clock Deskewing Pll Using Analog Phase Interpolation (Article)
Subject: Charge Pump , Clock Buffer
Author: Adrian Maxim     
page:      110 - 131
Analog Circuits In Ultra-Deep-Submicron Cmos (Article)
Subject: Analog Design , Breakdown Process
Author: Anne-Johan Annema      Bram Nauta     
page:      132 - 143
Millimeter-Wave Cmos Design (Article)
Subject: Cmos Millimeter Wave , Millimeter Wave
Author: Chinh H. Doan      S Emami     
page:      144 - 155
Sige Bipolar Trnsceiver Circuits Operating At 60 Ghz (Article)
Subject: Direct Conversion , Low-Noise Amplifier
Author: Brain A. Floyd      Scott K. Reynolds     
page:      156 - 167
A Nonvolatile Programmable Solid -Electrolyte Nanometer Switch (Article)
Subject: Crossbar
Author: Shunichi Kaeriyama      T Sakamoto     
page:      168 - 176
Cut-And Paste Customization Of Oprganic Fetintegratred Circuit And Its Application To Electronic Artificial Skin (Article)
Subject: Area Sensor , Cut-And-Paste Customization , Dynamic Boosted-Gate
Author: Hiroshi Kawaguchi      Takao Someya     
page:      177 - 185
A 300-Mhz 25 A/ Mb-Leakage On-Chip Sram Module Featuring Process-Variation Immunity And Low-Leakage -Active Mode For Mobile -Phone Application Processor (Article)
Subject: Application Processor , Cellular Phone
Author: M Yamaoka      Yoshihiro Shinozaki     
page:      186 - 194
A 64-Bit Microprocessor In 130-Nm And 90-Nm Technologies With Power Management Features (Article)
Subject: Cmos Integrated Circuits , Microprocessors
Author: Norman J. Rohrer      Cedric Lichtenau     
page:      19 - 27
A 130-Nm Triple -Vt 9-Mb Third-Level On-Die Cache For The 1.7-Ghz Itanium 2 Processor (Article)
Subject: Circuit Design , Clock Distribution , Computer Architecture
Author: Jonathan Chang      Stefan Rusu     
page:      195 - 203
A 312-Mhz 16-Mb Random-Cycle Embedded Drammacro With A Power-Down Data Retention Mode For Mobile Applications (Article)
Subject: Cmos Memory Integrated Circuits
Author: Fukashi Morishita      Isamu Hayashi     
page:      204 - 212
A 500-Mhz Multi-Banked Compilable Dram Macro With Direct Write And Programmable Pipelining (Article)
Subject: Dram Macro
Author: Josef Barth      Darren Anand     
page:      213 - 222
A 1.6-Gb/S/Pin Double Data Rate Sdram With Wave-Pipelined Cas Latency Control (Article)
Subject: Bus Efficiency , Cas Latency
Author: Sang-Bo Lee      Seong-Jin Jang     
page:      223 - 232
A 3.6-Gb/S Point-To-Point Interface For Capacity-Scalable Memory Subsystems (Article)
Subject: Memory , Cmos , Dram
Author: Joseph Kennedy      Randy Mooney     
page:      233 - 244
A Cost-Efficient High-Performance Dynamic Tcam With Pipelined Hierarchical Searching And Shift Redundancy Architecture (Article)
Subject: Cmos , Embedded Dram , Network
Author: Hideyuki Noda      Kazunari Inoue     
page:      245 - 253
A 0.7-Fj/Bit/Search 2.2-Ns Search Time Hybrid - Type Tcam Architecture (Article)
Subject: Content-Addressable , Hidden Markov Model , High Speed
Author: Sungdae Choi      Kyomin Sohn     
page:      254 - 260
Architecture And Circuit Techniques For A 1.1-Ghz 16-Kb Reconfigurable Memory In 0.18-Um Cmos (Article)
Subject: Memory , Reconfigurable Logic
Author: Ken Mai      Elad Alon     
page:      261 - 275
A Design For A Minimium Hamming -Distance Search Using Asynchronous Digital Techniques (Article)
Subject: Asynchronous Circuits , Associative Memories
Author: Shigeru Nakahara      Takahiro Kawata     
page:      276 - 285
Dynamic Voltage And Frequency Management For A Low-Power Embedded Microprocessor (Article)
Subject: Delay Synthesizer , Dynamic Frequency Scaling
Author: Masakatsu Nakai      Satoshi Akui     
page:      28 - 35
A 0.9-V Itic Sbt-Based Embedded Nonvolatile Feram With A Reference Voltage Schemem And Multilayer Shielded Bit-Line Structure (Article)
Subject: Ferroelectric , Memory
Author: Kunisato Yamaoka      Shunichi Iwanari     
page:      286 - 292
A 0.18-Um 3.0-V 64-Mb Nonvolatile Phase-Transition Random Access Memory (Pram) (Article)
Subject: Phase Change , Phase-Transition
Author: Woo Yeong Cho      Beak-Hyung Cho     
page:      293 - 300
A 4-Mb 0.18-Um 1t1mtj Toggle Mram With Balanced Three Input Sensing Scheme And Locally Mirrored Unidirectional Write Drivers (Article)
Subject: Mram , Magnetic Memories
Author: Thomas Andre      Joseph J. Nahas     
page:      301 - 309
A 180-Mv Subthreshold Fft Processor Using A Minimium Energy Design Methodology (Article)
Subject: Cmos Digital Integrated Circuits, , Cmos Memory Integrated Circuits
Author: Alice Wang      Anantha Chandrakasan     
page:      310 - 319
A 28.8 Mb/S 4*4 Mimo 3g Cdma Receiver For Frequency Selective Channels (Article)
Subject: Adaptive Equalizers , Communication Terminals
Author: David Garrett      Graeme K Woodward     
page:      320 - 330
14440*1080 Pixel,30 Frames Per Second Motion-Jpeg 2000 Codec For Hd-Movie Transmission (Article)
Subject: Image Compression , Jpeg2000
Author: H Yamauchi      Shigeyuki Okada     
page:      331 - 341
A 0.18-Um Cmos Front-End Processor For A Blu-Ray Disc Recorder With An Adaptive Prml (Article)
Subject: Blu-Ray Disc
Author: Goang Seong Choi      Hyun Jeong Park     
page:      342 - 350
Low-Voltage Swing Logic Circuits For A Pentium 4 Processor Integer Core (Article)
Subject: Adders , Integrated Circuit , Microprocessor
Author: Daniel J. Deleganes      P. Baranyi     
page:      36 - 43
A 4-Ghz 300-Mw 64-Bit Integer Execution Alu With Dual Supply Voltages In 90-Nm Cmos (Article)
Subject: Arithmetic And Logic Unit(Alu) , Dual Supply Voltage , Semi-Dynamic Design
Author: Sanu K. Mahew      Mark A. Anders     
page:      44 - 51
A 4-Mb On Chip L2 Cache L2 Cache For A 90-Nm 1.6-Ghz 64-Bit Microprocessor (Article)
Subject: Cache Memories , Integrated Circuit Design , Manufacturability Analysis
Author: Hugh Mcintyre      Dennis Wendell     
page:      52 - 59
Mixed Body Bias Techniques With Fixed Vt And Ids Generation Circuits (Article)
Subject: Body Bias , Fluctuations
Author: Masaya Sumita      Shiro Sakiyama     
page:      60 - 66
An On-Chip Active Decoupling Circuit To Supress Crosstalk In Deep-Submicron Cmos Mixed-Signal Socs (Article)
Subject: Analog And Mixed Signal Integrated Circuits , Noise Coupling , Signal Integrity
Author: Toshiro Tsukada      Yasuyuki Hashimoto     
page:      67 - 79
8-Gb/S Source-Synchronous I/O Link With Adaptive Receiver Equalization Offset Cancellation And Clock De-Skew (Article)
Subject: Adaptive Equalizer , Analog Equalization
Author: James E. Jaussi      S. Balamurugan     
page:      80 - 88
A 4-Gb/S/Pin Low Power Memory I/O Interface Using Levelsimultaneous Bi-Directional Signaling (Article)
Subject: 4-Level , Dram , I/O , Impedance Control
Author: Jin-Hyun Kim      Woo-Seop Kim     
page:      89 - 101